When jitter resistance of devices under test (hereinafter, will be referred to as “DUTs”) is tested in semiconductor testers, it is necessary to add jitter to test patterns applied to the DUTs. Jitter generating circuits are used for this purpose (e.g., see patent document 1). In such a jitter generating circuit, by comparing the offset voltage of a sinusoidal wave and the output voltage of a ramp generator, sinusoidal fluctuations are provided at a time when a clock signal changes.
[Patent document 1] Japanese Patent Laid-Open No. 6-104708 (pp. 3 to 4, FIGS. 1 to 3)